On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

DOI10.1016/0167-9260(96)00005-3zbMath0875.68157OpenAlexW2023701305MaRDI QIDQ4332022

Linda Pagli, Amiya Nayak, Nicola Santoro

Publication date: 27 February 1997

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(96)00005-3

zbMATH Keywords

TestingFault toleranceSystolic arraysCatastrophic fault patterns

Mathematics Subject Classification ID

Computer system organization (68M99)

Related Items (5)

Counting the number of fault patterns in redundant VLSI arrays ⋮ Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links ⋮ An improved testing scheme for catastrophic fault patterns ⋮ Catastrophic faults in reconfigurable systolic linear arrays ⋮ On enumeration of catastrophic fault patterns

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