Testing CMOS combinational iterative logic arrays for realistic faults

DOI10.1016/S0167-9260(96)00000-4zbMath0900.68080MaRDI QIDQ4332045

Antonis Paschalis, Dimitris Nikolos, Dimitris Gizopoulos

Publication date: 27 February 1997

Published in: Integration (Search for Journal in Brave)

zbMATH Keywords

VLSI testingC-testabilityIterative logic arraysTest pattern generationCell fault modelLinear-testabilitySequential faults

Mathematics Subject Classification ID

Logic in artificial intelligence (68T27) Computer system organization (68M99)

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