A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer

DOI10.1016/J.JPDC.2008.03.004zbMath1243.68134OpenAlexW2083682931MaRDI QIDQ436815

Gerald R. Morris, Viktor K. Prasanna

Publication date: 26 July 2012

Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jpdc.2008.03.004

zbMATH Keywords

reductionsparse matrixFPGAiterative solverpipelineaccumulatorreconfigurable computer

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20) Computer system organization (68M99)

Uses Software

• SPARSKIT

Cites Work

• Methods of conjugate gradients for solving linear systems
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