Reconfiguring Arrays with Faults Part I: Worst-Case Faults

DOI10.1137/S0097539793255011zbMath0885.68011OpenAlexW2047724932MaRDI QIDQ4376192

Ramesh K. Sitaraman, Bruce M. Maggs, Richard John Cole

Publication date: 10 February 1998

Published in: SIAM Journal on Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1137/s0097539793255011

zbMATH Keywords

fault tolerancemesh networknetwork emulationarray-based network

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Formal languages and automata (68Q45) Mathematical problems of computer architecture (68M07) Reliability, testing and fault tolerance of networks and computer systems (68M15)

Related Items (4)

Catastrophic faults in reconfigurable systolic linear arrays ⋮ Real-time emulations of bounded-degree networks ⋮ Grid minors in damaged grids ⋮ Self-spanner graphs

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