A note on architectures for large-capacity CAMs
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Publication:4397101
DOI10.1016/S0167-9260(97)00010-2zbMath0894.68014MaRDI QIDQ4397101
Publication date: 30 June 1998
Published in: Integration (Search for Journal in Brave)
classificationassociative memoryVLSI architecturescontent-addressable memoryserial/parallel implementationstaxonomy for CAMs
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