Design and analysis of an optimal instruction-retry policy for TMR controller computers
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Publication:4406348
DOI10.1109/12.544478zbMath1057.68566OpenAlexW2110878481MaRDI QIDQ4406348
Publication date: 25 June 2003
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/12.544478
Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)
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