Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

DOI10.1109/12.364534zbMath1040.68530OpenAlexW2138530143MaRDI QIDQ4419636

Srikanth Venkataraman, Sybille Hellebrand, Bernard Courtois, Janusz Rajski, Steffen Tarnick

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://semanticscholar.org/paper/0da5591799d9fd6947f95362a29dba01d2dc30b1

zbMATH Keywords

decompressionmultiple-polynomial LFSRscan design

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

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A mixed-mode BIST scheme based on folding compression ⋮ The transformation between the Galois NLFSRs and the Fibonacci NLFSRs via semi-tensor product of matrices ⋮ Nonlinear Codes for Test Patterns Compression: The Old School Way ⋮ Randomness quality of permuted pseudorandom binary sequences ⋮ Novel way to research nonlinear feedback shift register

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