On fault simulation for synchronous sequential circuits

DOI10.1109/12.364543zbMath1040.68525OpenAlexW2074504800MaRDI QIDQ4419650

Irith Pomeranz, Sudhakar M. Reddy

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.364543

zbMATH Keywords

test strategythree-value logic

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

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