Test generation for path delay faults using binary decision diagrams

DOI10.1109/12.372035zbMath1040.68518OpenAlexW2105954189MaRDI QIDQ4419665

Prathima Agrawal, Debashis Bhattacharya, Vishwani D. Agrawal

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.372035

zbMATH Keywords

Boolean algebraic test generationredundant delay faultsrobust delay tests

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

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