Bit-level systolic array for fast exponentiation in GF(2/sup m/)

DOI10.1109/12.293263zbMath1042.68827OpenAlexW2125713877MaRDI QIDQ4419735

Chin-Liang Wang

Publication date: 1994

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.293263

zbMATH Keywords

VLSIfinite field exponentiationlimit field multiplication

Mathematics Subject Classification ID

Parallel algorithms in computer science (68W10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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