An architecture for tolerating processor failures in shared-memory multiprocessors

DOI10.1109/12.543705zbMath1057.68520OpenAlexW2160101196MaRDI QIDQ4420827

Peter Alan Lee, Michel Banâtre, Christine Morin, Philippe Joubert, Alain Gefflaut

Publication date: 1996

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://semanticscholar.org/paper/9fa314f7d1b3c0d645f98a469525727ee44945f4

zbMATH Keywords

fault tolerancebackward error recovery

Mathematics Subject Classification ID

Computer system organization (68M99) Reliability, testing and fault tolerance of networks and computer systems (68M15)

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