Simulation and generation of IDDQ tests for bridging faults in combinational circuits

DOI10.1109/12.543707zbMath1057.68525OpenAlexW2174547182MaRDI QIDQ4420830

Sreejit Chakravarty, Paul J. Thadikaran

Publication date: 1996

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.543707

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Reliability, testing and fault tolerance of networks and computer systems (68M15)

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