Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

DOI10.1109/12.537126zbMath1048.68968OpenAlexW2128702371MaRDI QIDQ4420848

James C. Harden, Daniel H. Linder

Publication date: 1996

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://semanticscholar.org/paper/074411af7e59ae11a9d27937750fe542d5f2cd50

zbMATH Keywords

asynchronous circuitryLevel-Encoded two-phase Dual-Rail

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

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