Augmented binary hypercube: a new architecture for processor management
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Publication:4420873
DOI10.1109/12.536241zbMath1058.68519OpenAlexW2166289312MaRDI QIDQ4420873
Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili
Publication date: 26 October 2003
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/12.536241
Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)
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