A new architecture for a parallel finite field multiplier with low complexity based on composite fields

DOI10.1109/12.508323zbMath1049.68501OpenAlexW1967380110MaRDI QIDQ4420885

Christof Paar

Publication date: 1996

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://semanticscholar.org/paper/324bf468d6ff9b530ffaf515d02b4b6c162f83f0

zbMATH Keywords

VLSI architecturepolynomial multiplicationbit parallel multiplicationKaratsuba Ofman algorithm

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

Related Items (5)

Scalable and systolic architecture for computing double exponentiation over \(\text{GF}(2^m)\) ⋮ Multiplexer implementation of low-complexity polynomial basis multiplier in \(\mathrm{GF}(2^m)\) using all one polynomial ⋮ Speedup of bit-parallel Karatsuba multiplier in \(\mathrm{GF}(m^2)\) generated by trinomials ⋮ Finite field trigonometric transforms ⋮ A survey of some recent bit-parallel \(\mathrm{GF}(2^n)\) multipliers

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