Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility

DOI10.1080/002075400188627zbMath0944.90554OpenAlexW2170909621MaRDI QIDQ4497252

W. Matthew Carlyle, John W. Fowler, Kraig R. Knutson

Publication date: 22 August 2000

Published in: International Journal of Production Research (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/002075400188627

Mathematics Subject Classification ID

Production models (90B30)

Related Items (4)

Lot-order assignment applying priority rules for the single-machine total tardiness scheduling with nonnegative time-dependent processing times ⋮ Evaluation of heuristics for a class-constrained lot-to-order matching problem in semiconductor manufacturing ⋮ Forming and scheduling jobs with capacitated containers in semiconductor manufacturing: Single machine problem ⋮ Semiconductor lot allocation using robust optimization

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