Modeling of interconnection subsystems for massively parallel computers

DOI10.1016/S0166-5316(01)00058-XzbMath1013.68048OpenAlexW1974650195WikidataQ126321852 ScholiaQ126321852MaRDI QIDQ4538663

J. A. Gregorio, F. Vallejo, Ramón Beivide

Publication date: 14 July 2002

Published in: Performance Evaluation (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0166-5316(01)00058-x

zbMATH Keywords

simulationperformance evaluationstochastic Petri netsmassively parallel computershardware message routerinterconnection subsystem

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

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