A survey on multi-net global routing for integrated circuits

DOI10.1016/S0167-9260(01)00020-7zbMath0995.68197WikidataQ126553730 ScholiaQ126553730MaRDI QIDQ4539951

Sachin S. Sapatnekar, Jiang Hu

Publication date: 15 July 2002

Published in: Integration (Search for Journal in Brave)

zbMATH Keywords

VLSI circuitsglobal routing

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Related Items (4)

A fast heuristic algorithm for the maximum concurrent \(k\)-splittable flow problem ⋮ A PSO-based timing-driven octilinear Steiner tree algorithm for VLSI routing considering bend reduction ⋮ Unnamed Item ⋮ A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing

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