Fault-tolerant graphs for tori

DOI<link itemprop=identifier href="https://doi.org/10.1002/(SICI)1097-0037(199810)32:3<181::AID-NET2>3.0.CO;2-G" /><181::AID-NET2>3.0.CO;2-G 10.1002/(SICI)1097-0037(199810)32:3<181::AID-NET2>3.0.CO;2-GzbMath1015.68009OpenAlexW1973304476MaRDI QIDQ4540075

Toshinori Yamada, Shuichi Ueno

Publication date: 21 July 2002

Full work available at URL: https://doi.org/10.1002/(sici)1097-0037(199810)32:3<181::aid-net2>3.0.co;2-g

zbMATH Keywords

fault-tolerant multiprocessor interconnection networks

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Graph algorithms (graph-theoretic aspects) (05C85)

Related Items (1)

Optimal 1-edge fault-tolerant designs for ladders.

This page was built for publication: Fault-tolerant graphs for tori