Hierarchical fault diagnosis of analog integrated circuits

DOI10.1109/81.940182zbMath1002.94056OpenAlexW2124965808MaRDI QIDQ4540168

W. Tenten, Chung Kin Ho, Friedman Eberhardt, P. Shepherd

Publication date: 21 July 2002

Published in: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/81.940182

zbMATH Keywords

fault diagnosisdiagnosis algorithmhierarchical systemsfault locationanalog integrated circuitslarge scale circuitsintegrated circuit testing

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Fault detection; testing in circuits and networks (94C12) Applications of graph theory to circuits and networks (94C15)

Related Items (2)

A classical parameter identification method and a modern test generation algorithm ⋮ Application of extension neural network type-1 to fault diagnosis of electronic circuits

This page was built for publication: Hierarchical fault diagnosis of analog integrated circuits