N latency 2N I/O‐bandwidth 2D‐array matrix multiplication algorithm

DOI10.1108/03321640210423298zbMath1005.65043OpenAlexW2088599637MaRDI QIDQ4542827

Abdelkrim Kamel Oudjida, S. Titr, M. Hamarlain

Publication date: 11 February 2003

Published in: COMPEL - The international journal for computation and mathematics in electrical and electronic engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1108/03321640210423298

zbMATH Keywords

parallel computationmatrix multiplication algorithmsystolic approach

Mathematics Subject Classification ID

Cites Work

• Unnamed Item
• A note on Boolean matrix multiplication
• A practical algorithm for Boolean matrix multiplication
• An even faster systolic array for matrix multiplication
• A two-layered mesh array for matrix multiplication
• Gaussian elimination is not optimal
• A family of new efficient arrays for matrix multiplication
• Combinatorial Matrix Theory

This page was built for publication: N latency 2N I/O‐bandwidth 2D‐array matrix multiplication algorithm