Near-optimal PLL design for decision-feedback carrier and timing recovery

DOI10.1109/26.950353zbMath1010.93529OpenAlexW2475841182MaRDI QIDQ4553113

Dan Raphaeli, Oded Yaniv

Publication date: 4 May 2003

Published in: IEEE Transactions on Communications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/26.950353

zbMATH Keywords

phase locked loopdecision delayPLL loop filterssynchronization loops

Mathematics Subject Classification ID

Digital control/observation systems (93C62) Communication theory (94A05)

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