Dynamic pipeline design of an adaptive binary arithmetic coder

DOI10.1109/82.964994zbMath1009.68048OpenAlexW2148156172MaRDI QIDQ4553221

Yeu Horng Shiau, Jer Min Jou, Ren der Chen, Shiann Rong Kuang

Publication date: 25 November 2002

Published in: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL: https://semanticscholar.org/paper/86b4cb140a7559f6946dcb8a109846206eabb8a0

zbMATH Keywords

data compressionarithmetic codingVLSI architecturedynamic pipeline

Mathematics Subject Classification ID

Computer science aspects of computer-aided design (68U07) Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30)

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