Localizing Faults in Simulink/Stateflow Models with STL

DOI10.1145/3178126.3178131zbMath1409.68168OpenAlexW2796327418WikidataQ124212529 ScholiaQ124212529MaRDI QIDQ4561453

Thomas Ferrère, Niveditha Manjunath, Ezio Bartocci, Dejan Ničković

Publication date: 6 December 2018

Published in: Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (part of CPS Week) (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1145/3178126.3178131

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Temporal logic (03B44)

Related Items (2)

A survey of challenges for runtime verification from advanced application domains (beyond software) ⋮ Survey on mining signal temporal logic specifications

Uses Software

• Matlab
• Simulink
• StateFlow
• Breach
• AMT

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