Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero

DOI10.1109/TC.2007.70750zbMath1390.65191OpenAlexW2129841790MaRDI QIDQ4564236

S. Boussakta, Riyaz A. Patel, Mohammed Benaissa

Publication date: 12 June 2018

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2007.70750

Mathematics Subject Classification ID

Parallel numerical computation (65Y05) Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

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