Diminished-one modulo 2/sup n/+1 adder design

DOI10.1109/TC.2002.1146705zbMath1391.94804OpenAlexW2120088694MaRDI QIDQ4571229

Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos

Publication date: 9 July 2018

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2002.1146705

Mathematics Subject Classification ID

Cryptography (94A60) Mathematical problems of computer architecture (68M07) Arithmetic codes (94B40)

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