Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

DOI10.1109/TSP.2011.2109953zbMath1392.68448MaRDI QIDQ4572917

B. K. Mohanty, Pramod Kumar Meher

Publication date: 18 July 2018

Published in: IEEE Transactions on Signal Processing (Search for Journal in Brave)

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)

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