Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

DOI10.1142/S0219749918500168zbMath1396.81070MaRDI QIDQ4584406

Anita Pal, Arindam Biswas, Heranmoy Maity, Anup Kumar Bhattacharjee

Publication date: 3 September 2018

Published in: International Journal of Quantum Information (Search for Journal in Brave)

zbMATH Keywords

shift registerquantum costgarbage outputsreversible logic gate

Mathematics Subject Classification ID

Quantum computation (81P68) Mathematical problems of computer architecture (68M07)

Related Items (1)

Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

Cites Work

• NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS

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