A Selective Trigger Scan Architecture for VLSI Testing

DOI10.1109/TC.2007.70806zbMath1373.68025MaRDI QIDQ4589553

Zainalabedin Navabi, Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi

Publication date: 10 November 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Reliability, testing and fault tolerance of networks and computer systems (68M15)

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