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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder - MaRDI portal

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

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Publication:4590345

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DOI10.1109/TCSI.2004.838266zbMath1374.94865MaRDI QIDQ4590345

Man Guo, M. Omair Ahmad, M. N. S. Swamy, ChunYan Wang

Publication date: 20 November 2017

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Mathematics Subject Classification ID

Decoding (94B35)

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