Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

DOI10.1109/TCSI.2005.862074zbMath1374.94879MaRDI QIDQ4590538

Hui Liu, C. J. Richard Shi, Lei Yang

Publication date: 20 November 2017

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Mathematics Subject Classification ID

Decoding (94B35)

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