Novel parity-preserving designs of reversible 4-bit comparator

DOI10.1007/S10773-013-1904-9zbMath1297.81055OpenAlexW1979741820MaRDI QIDQ461832

Yun-xiang Sun, Liang-min Guo, Hong-tao Wang, Fu-long Chen, Xue-mei Qi

Publication date: 15 October 2014

Published in: International Journal of Theoretical Physics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10773-013-1904-9

zbMATH Keywords

simulationFVGB block and CPGB blockparity-preservingreversible comparatorTVG gate and CPG gate

Mathematics Subject Classification ID

Quantum computation (81P68)

Related Items (2)

Novel designs of nanometric parity preserving reversible compressor ⋮ Novel designs of quantum reversible counters

Cites Work

• On figures of merit in reversible and quantum logic designs
• Conservative logic
• Optimization approaches for designing a novel 4-bit reversible comparator
• Irreversibility and Heat Generation in the Computing Process
• Logical Reversibility of Computation

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