Process specification and verification

DOI10.1007/3-540-61228-9_90zbMath1412.68137OpenAlexW1605782337MaRDI QIDQ4645279

Klaus Barthelmann

Publication date: 10 January 2019

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/3-540-61228-9_90

zbMATH Keywords

temporal logicgraph grammarpredicate logicprecise formulagraph expression

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Grammars and rewriting systems (68Q42)

Cites Work

• A calculus of mobile processes. II
• Plain CHOCS. A second generation calculus for higher order processes
• A comparison of compatible, finite, and inductive graph properties
• Amalgamation of graph transformations: a synchronization mechanism
• Graph expressions and graph rewritings
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