PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

DOI10.2478/s13537-013-0112-2zbMath1409.94902OpenAlexW2034282686MaRDI QIDQ469056

J. Herrera, Sumit K. Garg

Publication date: 10 November 2014

Published in: Central European Journal of Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.2478/s13537-013-0112-2

zbMATH Keywords

cryptographyFPGAthroughputAESASICparallel sub-pipelined

Mathematics Subject Classification ID

Cryptography (94A60)

Cites Work

• Key Recovery Attacks of Practical Complexity on AES-256 Variants with up to 10 Rounds
• Cryptanalysis of Block Ciphers with Overdefined Systems of Equations
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