On an Optimally Fault-Tolerant Multiprocessor Network Architecture

DOI10.1109/TC.1987.1676947zbMath0617.68038OpenAlexW1858317823MaRDI QIDQ4727426

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Publication date: 1987

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1987.1676947

zbMATH Keywords

connectivityregular digraphsshuffle-exchange graphoptimal fault tolerancefault-tolerant networkmultiprocessor network

Mathematics Subject Classification ID

Deterministic network models in operations research (90B10) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Applications of graph theory to circuits and networks (94C15) Theory of software (68N99)

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