scientific article; zbMATH DE number 1903354

zbMath1010.68711MaRDI QIDQ4804897

Tomoya Kitai, Tomohiro Yoneda, Chris Myers

Publication date: 1 May 2003

Full work available at URL: http://link.springer.de/link/service/series/0558/bibs/2404/24040195.htm

Title: zbMATH Open Web Interface contents unavailable due to conflicting licenses.

zbMATH Keywords

Failure analysisTiming constraintsTimed circuitsTrace theoretic verification

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Fault detection; testing in circuits and networks (94C12) Specification and verification (program logics, model checking, etc.) (68Q60) Reliability, testing and fault tolerance of networks and computer systems (68M15)

Related Items (4)

Reconciling fault-tolerant distributed computing and systems-on-chip ⋮ Parameter synthesis for hierarchical concurrent real-time systems ⋮ An Inverse Method for Parametric Timed Automata ⋮ Full simulation coverage for SystemC transaction-level models of systems-on-a-chip

Uses Software

• VINAS-P

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