FOLDING TRANSFORMATIONS ON SYSTOLIC AND VLSI PROCESSOR ARRAYS

DOI10.1080/10637199408915467zbMath1049.68968OpenAlexW2009513926MaRDI QIDQ4820052

Marjan Gušev, David J. Evans

Publication date: 6 October 2004

Published in: Parallel Algorithms and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/10637199408915467

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Numerical algorithms for specific classes of architectures (65Y10)

Related Items (1)

THE MAGIC OF INTERLOCKING PROPERTY: FAST SYSTOLIC DESIGN

Cites Work

• Unnamed Item
• Implementation of folding transformations on linear VSLI processor arrays
• Triangular systolic arrays for matrix product and factorisation
• On the Analysis and Synthesis of VLSI Algorithms

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