MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION

DOI10.1080/10637199508915530zbMath1049.68552OpenAlexW2049284689MaRDI QIDQ4820129

E. P. Papadopoulou, Yiannis G. Saridakis

Publication date: 6 October 2004

Published in: Parallel Algorithms and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/10637199508915530

Mathematics Subject Classification ID

Computer system organization (68M99)

Related Items (1)

MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION

Cites Work

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• Convergence of parallel multisplitting iterative methods for M-matrices
• Parallel algorithms and architectures for multisplitting iterative methods
• The Design of Optimal Systolic Arrays
• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
• Multi-Splittings of Matrices and Parallel Solution of Linear Systems
• Parallel Algorithms for Nonlinear Problems
• Solution of Partial Differential Equations on Vector and Parallel Computers
• A family of new efficient arrays for matrix multiplication
• Partitioned Matrix Algorithms for VLSI Arithmetic Systems
• MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION

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