A bit-serial floating-point unit for a massively parallel system on a chip

DOI10.1080/10637190410001725454zbMath1087.68502OpenAlexW1985623890MaRDI QIDQ4823578

Hans-Werner Lang, Bertil Schmidt, Manfred Schimmler

Publication date: 28 October 2004

Published in: Parallel Algorithms and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/10637190410001725454

zbMATH Keywords

Massively parallel processorsSystolic arraysBit-serial floating point unitsFloating-point unit

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)

Cites Work

• The instruction systolic array and its relation to other models of parallel computers
• Unnamed Item

This page was built for publication: A bit-serial floating-point unit for a massively parallel system on a chip