VLSI architectures for the discrete wavelet transform

DOI10.1109/82.386170zbMath0830.65148OpenAlexW2091920794MaRDI QIDQ4849385

Robert Michael Owens, Mohan Vishwanath, Mary Jane Irwin

Publication date: 4 February 1996

Published in: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/82.386170

zbMATH Keywords

discrete wavelet transformVLSI architectureslinear systolic arraysMallat's pyramid algorithmrecursive pyramid algorithm

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Numerical methods for discrete and fast Fourier transforms (65T50) Numerical algorithms for specific classes of architectures (65Y10)

Related Items (5)

High-performance 1-D and 2-D inverse DWT 5/3 filter architectures for efficient hardware implementation ⋮ Implementing single-scale wavelet transform processor with magnetostatic surface wave device ⋮ A novel FPGA architecture of a 2-D wavelet transform ⋮ Parallel implementation of wavelet-based image denoising on programmable PC-grade graphics hardware ⋮ VLSI architecture for forward discrete wavelet transform based on B-spline factorization

This page was built for publication: VLSI architectures for the discrete wavelet transform