Approximation scheme for restricted discrete gate sizing targeting delay minimization

DOI10.1007/S10878-009-9267-0zbMath1319.94121OpenAlexW1980050726MaRDI QIDQ491218

Shiyan Hu, Chen Liao

Publication date: 24 August 2015

Published in: Journal of Combinatorial Optimization (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10878-009-9267-0

zbMATH Keywords

combinatorial optimizationVLSI designfully polynomial time approximation schemedelay optimizationdiscrete gate sizing

Mathematics Subject Classification ID

Combinatorial optimization (90C27) Applications of graph theory to circuits and networks (94C15)

Uses Software

• TILOS

Cites Work

• An improved FPTAS for Restricted Shortest Path.
• Approximation Schemes for the Restricted Shortest Path Problem
• Chebyshev's approximation algorithms and applications

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