Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform

DOI10.1007/978-3-642-36334-4_9zbMath1305.94049OpenAlexW172652018MaRDI QIDQ4912493

Ingrid Verbauwhede, Dipanwita Roychowdhury, Santosh Ghosh

Publication date: 4 April 2013

Published in: Pairing-Based Cryptography – Pairing 2012 (Search for Journal in Brave)

Full work available at URL: https://www.cosic.esat.kuleuven.be/publications/article-2208.pdf

zbMATH Keywords

pairingprime fieldsfield programmable gate array (FPGA)pipelineKaratsuba multiplierMontgomery multiplication algorithmBarreto-Naehrig (BN) curvesIP core

Mathematics Subject Classification ID

Cryptography (94A60) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Mathematical problems of computer architecture (68M07) Applications to coding theory and cryptography of arithmetic geometry (14G50)

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