A systolic processor array for the quadrant interlocking elimination method

DOI10.1080/00207160008804920zbMath0957.65017OpenAlexW1997249648WikidataQ126244409 ScholiaQ126244409MaRDI QIDQ4951741

David J. Evans

Publication date: 11 March 2001

Published in: International Journal of Computer Mathematics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/00207160008804920

zbMATH Keywords

parallel computationquadrant interlocking elimination methodsystolic processor array

Mathematics Subject Classification ID

Parallel numerical computation (65Y05) Direct numerical methods for linear systems and matrix inversion (65F05)

Cites Work

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• A modification of the quadrant interlocking factorisation parallel method

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