Short Complete Fault Detection Tests for Logic Networks with Fan-In Two

DOI10.1134/S1990478919010137zbMath1438.94089OpenAlexW2942341050WikidataQ128024278 ScholiaQ128024278MaRDI QIDQ4973245

Kirill A. Popkov

Publication date: 2 December 2019

Published in: Journal of Applied and Industrial Mathematics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1134/s1990478919010137

zbMATH Keywords

logic networkcomplete fault detection testarbitrary stuck-at fault

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Switching theory, applications of Boolean algebras to circuits and networks (94C11)

Related Items (3)

The length of a single fault detection test for constant-nonpreserving element insertions ⋮ Short single fault detection tests for logic networks under arbitrary faults of gates ⋮ Lower bound of the length of a single fault diagnostic test with respect to insertions of a mod-2 adder

Cites Work

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• Complete Fault Detection Tests of Length 2 for Logic Networks under Stuck-at Faults of Gates
• On Minimally Testable Logic Networks
• On the synthesis of circuits admitting complete fault detection test sets of constant length under arbitrary constant faults at the outputs of the gates

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