New Speed Records for Montgomery Modular Multiplication on 8-Bit AVR Microcontrollers

DOI10.1007/978-3-319-06734-6_14zbMath1288.94075OpenAlexW2200263712MaRDI QIDQ4981770

Zhe Liu, Johann Großschädl

Publication date: 24 June 2014

Published in: Progress in Cryptology – AFRICACRYPT 2014 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-319-06734-6_14

zbMATH Keywords

modular reductionmulti-precision arithmeticAVR architecturehybrid multiplicationSPA countermeasure

Mathematics Subject Classification ID

Cryptography (94A60) Mathematical problems of computer architecture (68M07)

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