Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits

DOI10.1134/S0005117915040104zbMath1327.94093MaRDI QIDQ500124

A. Yu. Matrosova, V. B. Lipskii

Publication date: 1 October 2015

Published in: Automation and Remote Control (Search for Journal in Brave)

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Related Items (1)

Constructing a sequence detecting robustly testable path delay faults in sequential circuits

Cites Work

• On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets
• Detection of Multiple Faults in Combinational Logic Networks
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