A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time <formula formulatype="inline"><tex Notation="TeX">$\Sigma\Delta$</tex> </formula> ADC for a Digital Closed-Loop Class-D Amplifier

DOI10.1109/TCSI.2014.2373971zbMath1468.94588OpenAlexW2206003861WikidataQ63412261 ScholiaQ63412261MaRDI QIDQ5007659

Andrea Baschirotto, Rémy Cellier, Angelo Nagari, Piero Malcovati, Achille Donida

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2014.2373971

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

This page was built for publication: A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time <formula formulatype="inline"><tex Notation="TeX">$\Sigma\Delta$</tex> </formula> ADC for a Digital Closed-Loop Class-D Amplifier