Area Efficient VLSI Architectures for Weak Signal Detection in Additive Generalized Cauchy Noise

DOI10.1109/TCSI.2020.2969985zbMath1468.94316OpenAlexW3006628743MaRDI QIDQ5008305

Siva Ram Krishna Vadali, Subrahmanyam Mula, Priyadip Ray, Saswat Chakrabarti

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2020.2969985

Mathematics Subject Classification ID

Parametric hypothesis testing (62F03) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Detection theory in information and communication theory (94A13)

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