Jitter Minimization in Digital PLLs with Mid-Rise TDCs

DOI10.1109/TCSI.2019.2959252zbMath1468.94940OpenAlexW2996914186MaRDI QIDQ5008363

Carlo Samori, Luca Avallone, Salvatore Levantino, Saleh Karman, Michael Peter Kennedy

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2019.2959252

Mathematics Subject Classification ID

Circuits in qualitative investigation and simulation of models (94C60)

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