A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process

DOI10.1109/TCSI.2012.2215781zbMath1468.94675OpenAlexW2144845516MaRDI QIDQ5008428

Young-Ho Kwak, Yong-Tae Kim, Chulwoo Kim, Sewook Hwang

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2012.2215781

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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